With the advent of technology, the size and working speed of memory core have increased dramatically in today's integrated circuits, and the integration of system-on-chip (SoC) becomes more and more popular. As the SOC design grows, demand for embedded memory also increases. The memory core in the SOC design normally has larger area than other cores, and its density is also higher than that of logic cores. Therefore, the memory yield often dominates the yield of a SoC chip. SoC chips usually have poor yield. An efficient method for improving the SoC yield is increasing the memory yield.
To improve the memory yield, efficient diagnosis and repair schemes are needed. The diagnosis scheme can detect the weakness of product and then modify design or process, and the repair scheme can replace the faulty cell with spare memory. Both of them can enhance the yield of memory cores. Embedded memory cores are widely used in SOC applications but they cannot be easily accessed from external circuitry. So these schemes should be realizable in circuit with acceptable area overhead. In other word, the area overhead of the built-in self-diagnosis (BISD) or built-in self-repair (BISR) should be low to reduce area penalty.
Testing of embedded memory is normally done by built-in self-test (BIST). A BIST scheme that also collects and exports the diagnostic data for subsequent on-line or off-line analysis has been called a BISD scheme. The exported diagnostic data can be used to, e.g., construct the bit-maps, identify the failure modes, repair the faulty cells, etc.
Frequently, the volume of diagnostic data of faulty memory cores is too large to be stored in the automatic test equipment (ATE), due to very limited space of the capture memory in a typical ATE. A solution to this problem is compression of diagnostic data. Recently, there are memory researches focusing on this subject. Some researchers define several frequently seen fail patterns, and compress the bit-maps based on these fail patterns. If the bit-maps relate to large memories, they are frequently compressed with fail patterns. The compression of output response from the BIST circuit can be found in the literature. The method is similar to signature analysis in logic BIST.
Fault-syndrome compression approaches have been proposed recently, where a partial Huffman-tree and other techniques are used to improve the compression ratio while maintaining a low BISD hardware cost.
FIG. 1 is a block diagram of a conventional BIST/BISD architecture that comprises three blocks, a controller 101, a sequencer 103 and a test pattern generator (TPG) 105. The controller 101 is the interface between the BIST/D and ATE. The sequencer 103 has a finite state machine (FSM), and is the main part of the BIST/D design. It controls the TPG 105 executing the test commands from the controller 101, and is also responsible for shifting out the fault syndromes. The TPG 105 has two main functions—decoding the test commands sent from the sequencer 103 and comparing the memory output with the expected data. The TPG 105 is thus highly dependent on the memory specifications, especially on the memory timing parameters and access modes. In physical design, it should be placed as close to the memory as possible to avoid possible timing violations. The sequencer 103 also becomes a complex circuit block if the BIST/D supports fail-pattern identification scheme.
FIG. 1 shows the input/output (I/O) signals MCK, MSI, MBC, MBS, MBO, MRD, MBR, and MSO, which represent the memory BISD-clock, memory BISD-scan-in, memory BISD-control, memory BISD mode selection, memory BISD-output, memory BISD-ready, memory BISD-reset, and memory BISD-scan-out signals, respectively.
Referring to FIG. 1, the operation of I/O signals is further explained herein below. For a synchronous RAM, MCK is usually the same as the memory clock so that at-speed test can be performed. The MSI input is for scan in test commands to the programmable BISD. The MBC signal controls the finite state machine (FSM) of the controller 101. Whether the system is in normal mode or BIST/BISD mode is determined by MBS. MBO outputs the test results, indicating whether the memory is good (1) or bad (0). As soon as the test process is finished, MRD goes high, else it stays low. The MBR signal is an asynchronous reset signal. Finally, MSO is used to scan out the error information for diagnosis or redundancy repair.
Diagnosis can help designers understand the weakness of the product, and redundancy repair can increase the yield of the product. The BISR design is the trend of the embedded memory, and there are many researches on this subject. Among them, the infrastructure IPs (IIPs) has been applied for yield enhancement. A memory core with BISR design is an important IIP. A BISR design with comprehensive real-time exhaustive search test and analysis method has been published. There are many types of redundancy structures. Among them, the word redundancy repair scheme was proposed early.
Another example is using a power-on repair BISR design with spare columns (1-D redundancy) only. The 2-D redundancy structure with segment partition and heuristic redundancy analysis (RA) algorithm was also studied. The authors applied a static and dynamic data-bin repair scheme or an on-line BISR design with a transparent BIST algorithm for SRAMs.
These redundancy repair researches focus on different applications, and they stress the importance of the BISR design.
FIG. 2 shows a typical BISR design which comprises three main blocks, BIST 201, built-in redundancy-analysis (BIRA) 203, and address reconfiguration (AR) 205.
The BIST 201 detects faults in the memory and exports the fault syndrome to the BIRA 203. The fault coverage of the BIST 201 depends on the test algorithms it implements. The fault syndrome generated by the BIST 201 contains the address of the faulty cell or word. The BIRA 203 receives the fault syndrome from the BIST 201 and analyzes the information using a built-in redundancy analysis algorithm. The BIRA 203 has two major functions: RA and spare element configuration.
The redundancy analysis algorithm is the main part of the BISR design, and it usually has two phases, must-repair phase and final spare allocation phase. The phase-1, must-repair phase, is used to identify the faulty rows or columns that must be repaired by spare rows or columns. In the second phase, the remaining faulty cells are repaired by the available spare elements not used in phase-1. This is normally done by simple heuristics. Most of the remaining faults in phase-2 are single-cell faults, and most of them are orthogonal with each other. The RA algorithm should be easy to implement, and be cost effective. Although exhaustive-search RA algorithms generate optimal spare allocation results, they are costly to implement and thus impractical.
Selection of an appropriate RA algorithm is highly related to the number of spare elements and their structure. This can be efficiently evaluated by a simulator which reports the repair rates for different RA algorithms and spare element configurations. Based on the repair rates, users will be able to select the most cost effective one for using in the BISR implementation.
The AR circuit is used to ‘repair’ the memory, i.e., it replaces the faulty cells with the fault-free spare ones. This is normally done by address remapping or address decoder reconfiguration (by, e.g., switches or fuses). If there is a non-volatile memory on chip, it can be used to store the reconfiguration information even when the power is off. Alternatively, power-on BIST and BISR can be used.
The complexity of an AR circuit depends partly on the spare structure, i.e., structure of spare rows, columns, words, blocks, etc. The complexity increases with the number of spare elements. Another important issue in the AR circuit design is performance penalty because it affects the access time of the memory during normal operation. The performance penalty due to address reconfiguration should be as low as possible.